Paul H. Siegel

Distinguished Professor, Department of Electrical and Computer Engineering
Endowed Chair, Center for Memory and Recording Research

Phone:   (858) 534-6210
Fax:         (858) 534-8059
Email:     psiegel@ucsd.edu
Office:   CMRR Room 305
Mailing Address:
Center for Memory and Recording Research
9500 Gilman Drive, Mail Code 0401
University of California, San Diego
La Jolla, CA 92093-0401

Selected Presentations
  1. “The Continuing Miracle of Information Storage Technology,” CMRR Shannon Symposium and Statue Dedication, La Jolla, CA, Oct. 15-16, 2001.

  2. “An Introduction to Error-Correcting Codes: The Virtues of Redundancy,” ECE Faculty-Staff Seminar, Feb. 28, 2003.

  3. “Capacity of Noiseless and Noisy Two-Dimensional Channels,” Workshop on Applications of Statistical Physics to Coding Theory, Center for Nonlinear Studies (CNLS), Los Alamos National Laboratory, Santa Fe, NM, Jan. 10-12, 2005.

  4. “Constrained Coding Techniques for Advanced Data Storage Devices,” Distinguished Speaker Seminar Series, ECE Department, University of Arizona, Tucson, AZ Feb. 8, 2005.

  5. “Applications of the Viterbi Algorithm in Data Storage Technology,” Viterbi Conference: Advancing Technology through Communications Sciences, University of Southern California, Mar. 8–9, 2005.

  6. “Information-Theoretic Limits of Two-Dimensional Optical Recording Channels,” Department of Information Engineering, University of Parma, May 19, 2006 and Communications Group, Politecnico di Torino, May 23, 2006.

  7. "An Introduction to Low-Density Parity-Check Codes," Tutorial Session - Research Review, Center for Wireless Communications, UC, San Diego, CA, May 31, 2007.

  8. Nanoengineering on a Vast Scale: The Wonders of Modern Information Storage Technology, Keynote Address - Qualcomm QTech Forum, Qualcomm, Incorporated, San Diego, CA, Nov. 6, 2007.

  9. "Writing More Than Once on a Write-Once Memory," Invited Talk - IEEE ICC 2012 Workshop on Emerging Data Storage Technologies,, Ottawa, Ontario, Canada, June 11, 2012.

  10. "Comparison of ECC Performance on Multilevel Flash Memories," Invited Talk - Asilomar Conference on Signals, Systems, and Computers (Session on Coding Theory for the Next-Generation Storage Systems), Pacific Grove, CA, November 6, 2012.

  11. "Row-by-Row Coding for Mitigation of Bitline Inter-cell Interference in MLC Flash Memories," Invited Talk - Workshop on Coding for Emerging Memories and Storage Technologies, Technion, Haifa, Israel, May 3, 2015.

  12. "Constrained Codes for Multilevel Flash Memories," Invited Talk - IEEE Information Theory Society Padovani Lecture, delivered at the 2015 North American School of Information Theory, La Jolla, CA, August 12, 2015.